1. Field of the Invention
The present invention is related to a semiconductor memory device adapted to carry out a test operation of the semiconductor memory device. The device according to the present invention is applicable to, for example, an EPROM.
2. Description of the Related Arts
In general, testing a semiconductor memory device upon manufacture is carried out by an IC tester and a probe. Among the various test modes used are a mode wherein all of the word lines or bit lines are selected, and a mode wherein a group of the word lines or bit lines is selected. These all-selection mode or group-selection mode tests are adopted to enhance the testing speed of the semiconductor memory device. The tests according to the above modes are usually carried out according to an all-selection or group-selection operation by programs stored in the IC tester.
However, in the prior art, in tests employing the all-selection or group-selection modes, usually the confirmation of whether or not the all-selection or group-selection signals are actually supplied to the device to be tested is not carried out. Accordingly, confirmation of whether or not an all-selection or a group-selection actually takes place is not carried out.
In addition, in the prior art, the selection of all of the word or bit lines, or the selection of a group of word or bit lines is confirmed by information obtained from the memory cell array. During this confirmation operation, however, it is necessary to store special information for the test in the memory cell and to read the stored special information. Such processes are complicated and inconvenient. Thus, a satisfactory method or system has not been established for realizing a reliable test including a complete test of the all-selection or group-selection of lines of a semiconductor memory device.